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Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process.

, , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 3044-3055 (2020)

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Survey of Scan Chain Diagnosis., , , and . IEEE Des. Test Comput., 25 (3): 240-248 (2008)Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (8): 1265-1273 (2013)Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator., , and . DAC, page 535-540. IEEE Computer Society Press, (1990)Differential Fault Simulation - a Fast Method Using Minimal Memory., and . DAC, page 424-428. ACM Press, (1989)Improve speed path identification with suspect path expressions., , , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Diagnosing timing related cell internal defects for FinFET technology., , , , and . VLSI-DAT, page 1-4. IEEE, (2015)A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders., and . IEEE Trans. Computers, 36 (7): 891-895 (1987)On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs., , , and . ETS, page 1-2. IEEE, (2014)Emulating and diagnosing IR-drop by using dynamic SDF., , , , and . ASP-DAC, page 511-516. IEEE, (2010)On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation., , , and . ATS, page 103-108. IEEE, (2021)