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Study of breakdown in STT-MRAM using ramped voltage stress and all-in-one maximum likelihood fit.

, , , , , , and . ESSDERC, page 146-149. IEEE, (2018)

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MTJ degradation in multi-pillar SOT-MRAM with selective writing., , , , , , , , and . IRPS, page 1-7. IEEE, (2023)Experimental extraction of BEOL composite equivalent thermal conductivities for application in self-heating simulations., , , and . ESSDERC, page 186-189. IEEE, (2018)MTJ degradation in SOT-MRAM by self-heating-induced diffusion., , , , , , , and . IRPS, page 4. IEEE, (2022)Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories., , , , , , , , , and . VLSI Technology and Circuits, page 375-376. IEEE, (2022)SOT-MRAM 300mm integration for low power and ultrafast embedded memories., , , , , , , , , and 9 other author(s). CoRR, (2018)Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution., , , , , , , , , and 3 other author(s). IRPS, page 1-5. IEEE, (2021)STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application., , , , , , , , , and 6 other author(s). IMW, page 1-4. IEEE, (2021)Understanding and empirical fitting the breakdown of MgO in end-of-line annealed MTJs., , , , , and . IRPS, page 1-5. IEEE, (2020)SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories., , , , , , , , , and 9 other author(s). VLSI Circuits, page 81-82. IEEE, (2018)Extended RVS characterisation of STT-MRAM devices: Enabling detection of AP/P switching and breakdown., , , , , , , , , and 1 other author(s). IRPS, page 5-1. IEEE, (2018)