Author of the publication

Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.

, , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (2): 109-130 (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Bounded Delay Timing Analysis of a Class of CSP Programs., and . Formal Methods Syst. Des., 11 (3): 265-294 (1997)The first asynchronous microprocessor: the test results., , , , and . SIGARCH Comput. Archit. News, 17 (4): 95-98 (1989)An improved benchmark suite for the ISPD-2013 discrete cell sizing contest., , , , , and . ISPD, page 168-170. ACM, (2013)CAD Directions for High Performance Asynchronous Circuits., , , , , , and . DAC, page 116-121. ACM Press, (1999)Efficient Timing Analysis of a Class of Petri Nets., and . CAV, volume 939 of Lecture Notes in Computer Science, page 423-436. Springer, (1995)An FPGA for Implementing Asynchronous Circuits., , , and . IEEE Des. Test Comput., 11 (3): 60-69 (1994)The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk)., , , , , , , , , and 3 other author(s). ICCAD, page 54:1-54:2. IEEE, (2020)Synthesis of asynchronous control circuits with automatically generated relative timing assumptions., , , and . ICCAD, page 324-331. IEEE Computer Society, (1999)Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries., and . DAC, page 83-88. ACM, (2011)Standard cell routing via boolean satisfiability., and . DAC, page 603-612. ACM, (2012)