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14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.

M. Kar, J. Silberman, S. Venkataramani, V. Srinivasan, B. Fleischer, J. Rubin, J. Lancaster, S. Lee, M. Cohen, M. Ziegler, N. Cao, S. Woodward, A. Agrawal, C. Zhou, P. Chatarasi, T. Gooding, M. Guillorn, B. Hekmatshoartabari, P. Jacob, R. Jain, S. Jain, J. Jung, K. Kim, S. Koswatta, M. Lutz, A. Mannari, A. Mathew, I. Nair, A. Ranjan, Z. Ren, S. Rider, T. Roewer, D. Satterfield, M. Schaal, S. Sen, G. Tellez, H. Tran, W. Wang, V. Zalani, J. Zhang, X. Zhang, V. Shah, R. Senger, A. Kumar, P. Lu, and L. Chang. ISSCC, page 254-256. IEEE, (2024)

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Designing for a gigahertz guTS integer processor.H. Hofstee, S. Dhong, D. Meltzer, K. Nowka, J. Silberman, J. Burns, S. Posluszny, and O. Takahashi. IEEE Micro, 18 (3): 66-74 (1998)Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.B. Flachs, S. Asano, S. Dhong, H. Hofstee, G. Gervais, R. Kim, T. Le, P. Liu, J. Leenstra, J. Liberty and 19 other author(s). IBM J. Res. Dev., 51 (5): 529-544 (2007)A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.A. Agrawal, S. Lee, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen and 34 other author(s). ISSCC, page 144-146. IEEE, (2021)The circuit design of the synergistic processor element of a CELL processor.O. Takahashi, R. Cook, S. Cottier, S. Dhong, B. Flachs, K. Hirairi, A. Kawasumi, H. Murakami, H. Noro, H. Oh and 3 other author(s). ICCAD, page 111-117. IEEE Computer Society, (2005)A 690 ps read-access latency register file for a GHz integer microprocessor.O. Takahashi, J. Silberman, S. Dhong, H. Hofstee, and N. Aoki. ICCD, page 6-10. IEEE Computer Society, (1998)A 1.0-GHz single-issue 64-bit powerPC integer processor.J. Silberman, N. Aoki, D. Boerstler, J. Burns, S. Dhong, A. Essbaum, U. Ghoshal, D. Heidel, H. Hofstee, K. Lee and 7 other author(s). IEEE J. Solid State Circuits, 33 (11): 1600-1608 (1998)Efficient AI System Design With Cross-Layer Approximate Computing.S. Venkataramani, X. Sun, N. Wang, C. Chen, J. Choi, M. Kang, A. Agarwal, J. Oh, S. Jain, T. Babinsky and 30 other author(s). Proc. IEEE, 108 (12): 2232-2250 (2020)"Timing closure by design, " a high frequency microprocessor design methodology.S. Posluszny, N. Aoki, D. Boerstler, P. Coulman, S. Dhong, B. Flachs, H. Hofstee, N. Kojima, O. Kwon, K. Lee and 7 other author(s). DAC, page 712-717. ACM, (2000)Power-Conscious Design of the Cell Processor's Synergistic Processor Element.O. Takahashi, S. Cottier, S. Dhong, B. Flachs, and J. Silberman. IEEE Micro, 25 (5): 10-18 (2005)A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.S. Lee, A. Agrawal, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen and 34 other author(s). IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)

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Disambiguation of "Silberman, Joel"

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14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.

Please choose a person to relate this publication to

Rosa Silberman

Walter Joel

Artur Joel

Feiga Joelsohn

Moritz Joel

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Silberman, Joel"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.

Please choose a person to relate this publication to

Rosa Silberman

Walter Joel

Artur Joel

Feiga Joelsohn

Moritz Joel

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.