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Dimensioning for power and performance under 10nm: The limits of FinFETs scaling., , , , , , , и . ICICDT, стр. 1-4. IEEE, (2015)Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes., , , , , , , , , и 5 other автор(ы). Microprocess. Microsystems, 39 (8): 1039-1051 (2015)STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes., , , , , , , , и . ESSDERC, стр. 97-100. IEEE, (2023)STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process., , , , , , , , и . ESSDERC, стр. 159-162. IEEE, (2013)5nm: Has the time for a device change come?, , , , , , , и . ISQED, стр. 275-277. IEEE, (2016)Lateral NWFET optimization for beyond 7nm nodes., , , , , , , , , и 3 other автор(ы). ICICDT, стр. 1-4. IEEE, (2015)Design Technology co-optimization for N10., , , , , , , , , и 18 other автор(ы). CICC, стр. 1-8. IEEE, (2014)Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM., , , , , , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (3): 183-187 (2010)PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology., , , , , , , , , и . VLSI Technology and Circuits, стр. 1-2. IEEE, (2023)Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications., , , , , , , и . ESSDERC, стр. 241-244. IEEE, (2022)