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Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits.

, , , and . J. Electron. Test., 16 (5): 443-451 (2000)

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Design of High-Level Test Language for Digital LSI., , and . ITC, page 508-513. IEEE Computer Society, (1983)Cascade Realization of 3-Input 3-Output Conservative Logic Circuits., and . IEEE Trans. Computers, 27 (3): 214-221 (1978)Realization of Minimum Circuits with Two-Input Conservative Logic Elements., and . IEEE Trans. Computers, 27 (8): 749-752 (1978)Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults., , and . FTCS, page 263-270. IEEE Computer Society, (1992)SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2561-2567 (2013)A Novel ATPG Method for Capture Power Reduction during Scan Testing., , , , , , and . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)Extended selection of switching target faults in CONT algorithm for test generation., and . J. Electron. Test., 1 (3): 183-189 (1990)Design of testing circuit and test generation for built-in current testing., , and . Syst. Comput. Jpn., 24 (5): 73-82 (1993)Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique., , and . Asian Test Symposium, page 94-99. IEEE Computer Society, (1996)An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits., , and . Asian Test Symposium, page 22-. IEEE Computer Society, (1997)