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Disambiguation of "Takamatsu, Yuzo"

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Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits.

, , , and . J. Electron. Test., 16 (5): 443-451 (2000)

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Yuzo Sugimoto

 

Other publications of authors with the same name

Test generation for scan design circuits with tri-state modules and bidirectional terminals., , , , and . DAC, page 71-78. ACM/IEEE, (1983)Multiple Fault Diagnosis by Sensitizing Input Pairs., , and . IEEE Des. Test Comput., 12 (3): 44-52 (1995)Addressing Defect Coverage through Generating Test Vectors for Transistor Defects., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (12): 3128-3135 (2009)Static test compaction for IDDQ testing of bridging faults in sequential circuits., , , and . Syst. Comput. Jpn., 31 (11): 41-50 (2000)Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints., , , , and . Asian Test Symposium, page 242-247. IEEE Computer Society, (2002)A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations., , and . VTS, page 64-69. IEEE Computer Society, (1999)An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets., , and . PRDC, page 275-282. IEEE Computer Society, (2002)Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits., , and . DELTA, page 431-433. IEEE Computer Society, (2002)On the fault diagnosis in the presence of unknown fault models using pass/fail information., , , , and . ISCAS (3), page 2987-2990. IEEE, (2005)Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (12): 3506-3513 (2008)