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Disambiguation of "Saluja, Kewal K."

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Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits.

, , , and . J. Electron. Test., 16 (5): 443-451 (2000)

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Heinz Kewald

Kewal Krishen Mehta

Aman K K Bhasin

K Kusterer

K Dugaev

 

Other publications of authors with the same name

Testing Computer Hardware through Data Compression in Space and Time., and . ITC, page 83-88. IEEE Computer Society, (1983)Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing., , , , , and . DAC, page 527-532. IEEE, (2007)An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive Faults., and . ITC, page 675-684. IEEE Computer Society, (1991)Analytic modeling of detection latency in mobile sensor networks., , and . IPSN, page 194-201. ACM, (2006)Modified T-Flip-Flop based scan cell for RAS., , , , and . European Test Symposium, page 113-118. IEEE Computer Society, (2010)Analysis and test procedures for NOR flash memory defects., and . Microelectron. Reliab., 48 (5): 698-709 (2008)Routing TCP Flows in Underwater Mesh Networks., , and . IEEE J. Sel. Areas Commun., 29 (10): 2022-2032 (2011)Delay Fault Testing of Processor Cores in Functional Mode., , , and . IEICE Trans. Inf. Syst., 88-D (3): 610-618 (2005)Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment., , , and . IEICE Trans. Inf. Syst., 96-D (6): 1323-1331 (2013)Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools., , , , and . IEICE Trans. Inf. Syst., 91-D (3): 690-699 (2008)