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A hardware based low temperature solution for VLSI testing using decompressor side masking., , , и . ISCAS, стр. 637-640. IEEE, (2015)Low power finite state machine synthesis using power-gating., , и . Integr., 44 (3): 175-184 (2011)Efficient Key-Gate Placement and Dynamic Scan Obfuscation Towards Robust Logic Encryption., , и . IEEE Trans. Emerg. Top. Comput., 9 (4): 2109-2124 (2021)An ATE assisted DFD technique for volume diagnosis of scan chains., , , и . DAC, стр. 31:1-31:6. ACM, (2013)Improving Security of Logic Encryption in Presence of Design-for-Testability Infrastructure., , и . ISCAS, стр. 1-5. IEEE, (2019)Runtime Mitigation of Packet Drop Attacks in Fault-tolerant Networks-on-Chip., , , и . CoRR, (2019)Application Mapping Onto Mesh-of-Tree Based Network-on-Chip Using Discrete Particle Swarm Optimization., , и . ISED, стр. 172-176. IEEE, (2012)A Deep Neural Network Augmented Approach for Fixed Polarity AND-XOR Network Synthesis., , , , , и . TENCON, стр. 2189-2193. IEEE, (2019)Confidence Based Power Aware Testing., , , и . ISED, стр. 62-66. IEEE, (2012)An ILP-based floorplan-aware path synthesis technique for Application-Specific NoC design., и . RAIT, стр. 543-548. IEEE, (2016)