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A Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model.

Z. Feng, B. Wang, Z. Zhang, A. Guo, и X. Si. APCCAS, стр. 524-527. IEEE, (2022)

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Si Gangyan

Si Yang

Zhongyi Si

Yuefang Si

Han Si

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A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips.X. Si, Y. Tu, W. Huang, J. Su, P. Lu, J. Wang, T. Liu, S. Wu, R. Liu, Y. Chou и 11 other автор(ы). IEEE J. Solid State Circuits, 56 (9): 2817-2831 (2021)A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips.J. Su, Y. Chou, R. Liu, T. Liu, P. Lu, P. Wu, Y. Chung, L. Hong, J. Ren, T. Pan и 15 other автор(ы). IEEE J. Solid State Circuits, 58 (3): 877-892 (марта 2023)A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference.H. Cai, Z. Bian, Y. Hou, Y. Zhou, J. Cui, Y. Guo, X. Tian, B. Liu, X. Si, Z. Wang и 2 other автор(ы). ISSCC, стр. 500-501. IEEE, (2023)15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.X. Si, Y. Tu, W. Huang, J. Su, P. Lu, J. Wang, T. Liu, S. Wu, R. Liu, Y. Chou и 17 other автор(ы). ISSCC, стр. 246-248. IEEE, (2020)16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.J. Su, Y. Chou, R. Liu, T. Liu, P. Lu, P. Wu, Y. Chung, L. Hung, J. Ren, T. Pan и 11 other автор(ы). ISSCC, стр. 250-252. IEEE, (2021)Evaluation Model for Current-Domain SRAM-based Computing-in-Memory Circuits.Y. Zhang, B. Wang, J. Chen, X. Chen, и X. Si. MCSoC, стр. 160-165. IEEE, (2023)34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.A. Guo, X. Chen, F. Dong, J. Chen, Z. Yuan, X. Hu, Y. Zhang, J. Zhang, Y. Tang, Z. Zhang и 13 other автор(ы). ISSCC, стр. 570-572. IEEE, (2024)14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS.W. Shan, K. Zhou, K. Li, Y. Du, Z. Chen, J. Qian, H. Ge, J. Yang, и X. Si. ISSCC, стр. 256-258. IEEE, (2024)A Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model.Z. Feng, B. Wang, Z. Zhang, A. Guo, и X. Si. APCCAS, стр. 524-527. IEEE, (2022)A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors.Z. Zhang, J. Chen, X. Si, Y. Tu, J. Su, W. Huang, J. Wang, W. Wei, Y. Chiu, J. Hong и 6 other автор(ы). A-SSCC, стр. 217-218. IEEE, (2019)

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