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A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (4): 755-766 (2019)LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2938-2951 (2020)Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (12): 5074-5085 (December 2023)Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator., , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 1752-1756 (2022)A Novel Built-In Self-Repair Scheme for 3D Memory., , , , and . IEEE Access, (2019)Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications., , , , , , and . J. Electron. Test., 37 (4): 489-502 (2021)Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (10): 3182-3187 (2022)A novel in-field TSV repair method for latent faults., , , and . IEICE Electron. Express, 15 (23): 20180873 (2018)Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs., , , , and . IEICE Electron. Express, 18 (2): 20200420 (2021)A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments., , , , , , and . ACM Great Lakes Symposium on VLSI, page 301-306. ACM, (2021)