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A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification.

, , , и . VTS, стр. 71-76. IEEE Computer Society, (2009)

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Esther Fujiwara

Hideo Baba

Hideo Ohashi

Hideo Andreas Baba

Hideo Ikezawa-Hanada

 

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The Complexity of Fault Detection Problems for Combinational Logic Circuits., и . IEEE Trans. Computers, 31 (6): 555-560 (1982)System-on-chip test scheduling with reconfigurable core wrappers., и . IEEE Trans. Very Large Scale Integr. Syst., 14 (3): 305-309 (2006)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , и . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints., , , , , и . J. Electron. Test., 28 (4): 511-521 (2012)SPIRIT: a highly robust combinational test generation algorithm., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (12): 1446-1458 (2002)New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency., , и . J. Electron. Test., 20 (3): 315-323 (2004)Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption., , и . J. Electron. Test., 18 (1): 55-62 (2002)Handling the pin overhead problem of DFTs for high-quality and at-speed tests., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (9): 1105-1113 (2002)Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System., , , и . WDAG, том 1320 из Lecture Notes in Computer Science, стр. 290-304. Springer, (1997)Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms., , и . DISC, том 5805 из Lecture Notes in Computer Science, стр. 172-173. Springer, (2009)