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ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration.

, , , , , , , , , and . IEEE J. Solid State Circuits, 58 (1): 243-255 (2023)

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Thermomechanical Stress-Aware Management for 3-D IC Designs., , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (9): 2678-2682 (2017)Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (10): 3041-3054 (2016)Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes., , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (1): 50-62 (2018)Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (1): 186-191 (2012)K-Hyperline Clustering-Based Color Image Segmentation Robust to Illumination Changes., , , , and . Symmetry, 10 (11): 610 (2018)Taming Unstructured Sparsity on GPUs via Latency-Aware Optimization., and . DAC, page 1-6. IEEE, (2020)3D-SWIFT: a high-performance 3D-stacked wide IO DRAM., , , , and . ACM Great Lakes Symposium on VLSI, page 51-56. ACM, (2014)NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs., , , , , and . IEEE Comput. Archit. Lett., 18 (1): 38-42 (2019)Overview of 3-D Architecture Design Opportunities and Techniques., , and . IEEE Des. Test, 34 (4): 60-68 (2017)Toward Increasing FPGA Lifetime., , , , , , and . IEEE Trans. Dependable Secur. Comput., 5 (2): 115-127 (2008)