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12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications., , , , , , , , , и 4 other автор(ы). ISSCC, стр. 210-211. IEEE, (2017)The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series., , , , , , , , , и 2 other автор(ы). IEEE J. Solid State Circuits, 42 (4): 846-852 (2007)A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell., , , и . IEEE J. Solid State Circuits, 54 (4): 1152-1160 (2019)Not-So-Latent Dirichlet Allocation: Collapsed Gibbs Sampling Using Human Judgments.. Mturk@HLT-NAACL, стр. 131-138. Association for Computational Linguistics, (2010)Comparison of child-human and child-computer interactions based on manual annotations., , , и . WOCCI, стр. 49-54. ISCA, (2009)A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache., , , , и . ISSCC, стр. 315-324. IEEE, (2006)F2: 3D stacking technologies for image sensors and memories., , , , , и . ISSCC, стр. 512-513. IEEE, (2014)A 16Kb Antifuse One-Time-Programmable Memory in 5nm High-K Metal-Gate Fin-FET CMOS Featuring Bootstrap High Voltage Scheme, Read Endpoint Detection and Pseudo-Differential Sensing., , , , , , , , , и 1 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2021)EE5: When will we stop driving our cars?, , , , и . ISSCC, стр. 524. IEEE, (2017)Software-controlled fault tolerance., , , , , и . ACM Trans. Archit. Code Optim., 2 (4): 366-396 (2005)