Author of the publication

Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits.

, , , and . LATW, page 59-64. IEEE, (2000)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Design theory and implementation for low-power segmented bus systems., , , , and . ACM Trans. Design Autom. Electr. Syst., 8 (1): 38-54 (2003)DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip., , and . DAC, page 849-852. ACM, (2006)Fault simulation and response compaction in full scan circuits using HOPE., , , , , and . IEEE Trans. Instrumentation and Measurement, 54 (6): 2310-2328 (2005)High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (3): 1169-1173 (2016)Turbo1500: Core-Based Design for Test and Diagnosis., , , , , , , , , and 5 other author(s). IEEE Des. Test Comput., 26 (1): 26-35 (2009)On random testing for combinational circuits with a high measure of confidence., and . IEEE Trans. Syst. Man Cybern., 22 (4): 748-754 (1992)Delay Fault Coverage Enhancement Using Variable Observation Times., , and . J. Electron. Test., 11 (2): 131-146 (1997)Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis., , , and . VLSI Design, 12 (4): 457-474 (2001)A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (3): 374-384 (1995)Pseudorandom test-length analysis using differential solutions., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (7): 815-825 (1996)