( en | de | ru )

 

Disambiguation of "Kim, Woo-Seop"

Author of the publication

copydeleteadd this publication to your clipboard
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.

, , , , , , , , , , , , , , , , , , and . ISSCC, page 527-536. IEEE, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Wan-Seop Kim

Jin-Seop Kim

Jong-Woo Kim

Kwang-Woo Kim

Jong-Woo Kim

 

Other publications of authors with the same name

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 44 (11): 2987-2998 (2009)An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 42 (1): 193-200 (2007)Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module., , , , , , , and . SoCC, page 343-348. IEEE, (2013)A control network architecture based on EIA-709.1 protocol for power line data communications., , , , and . IEEE Trans. Consumer Electronics, 48 (3): 650-655 (2002)A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling., , , , , , and . IEEE J. Solid State Circuits, 40 (1): 89-101 (2005)A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 40 (1): 233-244 (2005)Review of Memory RAS for Data Centers., , , and . IEEE Access, (2023)An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme., , , , , , , , , and 9 other author(s). ISSCC, page 527-536. IEEE, (2006)A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 45 (4): 880-888 (2010)A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter., , , , , , and . IEEE J. Solid State Circuits, 41 (1): 127-134 (2006)