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Disambiguation of "Jang, Young-Chan"

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An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.

, , , , , , , , , , , , , , , , , , and . ISSCC, page 527-536. IEEE, (2006)

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Young Jang Kim

Chan-Young Park

Christopher Young

Grady Leon Young

Charlotte Young

 

Other publications of authors with the same name

An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1386-1396 (2017)A 1 V 200 kS/s 10-bit Successive Approximation ADC for a Sensor Interface., , and . IEICE Trans. Electron., 94-C (11): 1798-1801 (2011)A 2-Gb/s CMOS SLVS Transmitter with Asymmetric Impedance Calibration for Mobile Interfaces., and . IEICE Trans. Electron., 97-C (8): 837-840 (2014)A 3.0 Gsymbol/s/lane MIPI C-PHY Receiver with Adaptive Level-Dependent Equalizer for Mobile CMOS Image Sensor., , and . Sensors, 21 (15): 5197 (2021)An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme., , , , , , , , , and 9 other author(s). ISSCC, page 527-536. IEEE, (2006)BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 44 (11): 2987-2998 (2009)An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 42 (1): 193-200 (2007)A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2., , , , and . IEEE Trans. Consumer Electronics, 63 (3): 209-215 (2017)A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface., and . IEEE Trans. Consumer Electronics, 65 (4): 484-492 (2019)A Bootstrapped Analog Switch with Constant On-Resistance., , , and . IEICE Trans. Electron., 94-C (6): 1069-1071 (2011)