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O for DRAM Application With DIMM Channel.

Y. Jang, H. Chung, Y. Choi, H. Park, J. Kim, S. Lim, J. Sunwoo, M. Park, H. Kim, S. Kim, Y. Lee, W. Kim, J. Lee, J. Yoo, and C. Kim. IEEE J. Solid State Circuits, 44 (11): 2987-2998 (2009)

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Andreas Choi

Chiwon Choi

Jinsub Choi

Youngmi Choi

Carmen Choi

Other publications of authors with the same name

A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth.Y. Choi, I. Song, M. Park, H. Chung, S. Chang, B. Cho, J. Kim, Y. Oh, D. Kwon, J. Sunwoo and 20 other author(s). ISSCC, page 46-48. IEEE, (2012)A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE.H. Jin, J. Byun, H. Cho, H. Yoon, J. Park, K. Kim, Y. Choi, J. Choi, H. Ko, and S. Lee. A-SSCC, page 1-3. IEEE, (2021)VSCHH 2023: A Benchmark for the View Synthesis Challenge of Human Heads.Y. Jang, J. Zheng, J. Song, H. Dhamo, E. Pérez-Pellitero, T. Tanay, M. Maggioni, R. Shaw, S. Catley-Chandar, Y. Zhou and 27 other author(s). ICCV (Workshops), page 1113-1120. IEEE, (2023)A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory.C. Kim, D. Kim, W. Jeong, H. Kim, I. Park, H. Park, J. Lee, J. Park, Y. Ahn, J. Lee and 20 other author(s). IEEE J. Solid State Circuits, 53 (1): 124-133 (2018)Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM.J. Ko, J. Kim, Y. Choi, H. Park, and S. Jung. IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (8): 2091-2102 (2015)A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW.H. Chung, B. Jeong, B. Min, Y. Choi, B. Cho, J. Shin, J. Kim, J. Sunwoo, J. min Park, Q. Wang and 25 other author(s). ISSCC, page 500-502. IEEE, (2011)A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics.H. Yoon, W. Jung, J. Park, J. Byun, H. Jin, H. Cho, Y. Kim, B. Lim, Y. Cho, Y. Choi and 4 other author(s). ESSCIRC, page 463-466. IEEE, (2021)Documenting Computing Environments for Reproducible Experiments.J. Chuah, M. Deeds, T. Malik, Y. Choi, and J. Goodall. PARCO, volume 36 of Advances in Parallel Computing, page 756-765. IOS Press, (2019)A Time-Based PAM-4 Transceiver Using Single Path Decoder and Fast-Stochastic Calibration Techniques.D. Yoon, H. Junsen, K. Baek, Y. Choi, J. Choi, and T. Kim. A-SSCC, page 1-3. IEEE, (2023)A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor.H. Kim, J. Lee, J. Lim, J. Boo, H. Kim, S. Park, Y. Choi, J. Choi, and G. Ahn. ISOCC, page 235-236. IEEE, (2022)

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Disambiguation of "Choi, Youngdon"

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BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel.

Please choose a person to relate this publication to

Andreas Choi

Chiwon Choi

Jinsub Choi

Youngmi Choi

Carmen Choi

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Choi, Youngdon"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel.

Please choose a person to relate this publication to

Andreas Choi

Chiwon Choi

Jinsub Choi

Youngmi Choi

Carmen Choi

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel.