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Disambiguation of "Park, Dukha"

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An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.

, , , , , , , , , , , , , , , , , , and . ISSCC, page 527-536. IEEE, (2006)

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Sungjune Park

Rosemary Park

Jinhyung Park

Kwan Park

June Park

 

Other publications of authors with the same name

A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 45 (4): 880-888 (2010)22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process., , , , , , , , , and 29 other author(s). ISSCC, page 382-384. IEEE, (2020)A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 55 (1): 157-166 (2020)An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme., , , , , , , , , and 9 other author(s). ISSCC, page 527-536. IEEE, (2006)An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques., , , , , , , , , and 18 other author(s). IEEE J. Solid State Circuits, 56 (1): 212-224 (2021)A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power., , , , , , , , , and 20 other author(s). ISSCC, page 378-380. IEEE, (2019)