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A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2011)Efficient and Effective Methods for Mixed Precision Neural Network Quantization for Faster, Energy-efficient Inference., , , , and . CoRR, (2023)Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores., , , , , , , , , and 6 other author(s). IJCNN, page 1-10. IEEE, (2013)A Low Power, Fully Event-Based Gesture Recognition System., , , , , , , , , and 6 other author(s). CVPR, page 7388-7397. IEEE Computer Society, (2017)11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip., , , , , , , , , and 22 other author(s). ISSCC, page 214-215. IEEE, (2024)Learned Step Size quantization., , , , and . ICLR, OpenReview.net, (2020)Cognitive computing programming paradigm: A Corelet Language for composing networks of neurosynaptic cores., , , , , , , , , and 4 other author(s). IJCNN, page 1-10. IEEE, (2013)The cat is out of the bag: cortical simulations with 109 neurons, 1013 synapses., , , and . SC, ACM, (2009)Compass: a scalable simulator for an architecture for cognitive computing., , , , , , , , and . SC, page 54. IEEE/ACM, (2012)Binding sparse spatiotemporal patterns in spiking computation., , and . IJCNN, page 1-9. IEEE, (2010)