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22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , и . ISSCC, стр. 334-336. IEEE, (2020)

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Eunkyong Oh

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A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization., , , , , , , , , и 39 other автор(ы). ISSCC, стр. 444-446. IEEE, (2022)13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization., , , , , , , , , и 38 other автор(ы). ISSCC, стр. 238-240. IEEE, (2024)A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization., , , , , , , , , и 29 other автор(ы). IEEE J. Solid State Circuits, 58 (1): 256-269 (2023)18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface., , , , , , , , , и 12 other автор(ы). ISSCC, стр. 318-319. IEEE, (2016)High bandwidth memory(HBM) with TSV technique., , , , , , , , , и 9 other автор(ы). ISOCC, стр. 181-182. IEEE, (2016)22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST., , , , , , , , , и 27 other автор(ы). ISSCC, стр. 334-336. IEEE, (2020)