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10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion.

F. Tesolin, S. Dartizio, G. Castoro, F. Buccoleri, M. Rossoni, D. Cherniak, C. Samori, A. Lacaita, and S. Levantino. ISSCC, page 198-200. IEEE, (2024)

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Francesco Bettella

Protein secondary structure prediction using optimized scoring functions: a comparative statistical methodF. Bettella. FU Berlin, (2009)

Francesco Solimena

Francesco Pinosa

Francesco Knechtli

Francesco Virili

Other publications of authors with the same name

A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.S. Dartizio, F. Tesolin, G. Castoro, F. Buccoleri, L. Lanzoni, M. Resson, D. Cherniak, L. Bertulessi, C. Samori, A. Lacaita and 1 other author(s). ISSCC, page 78-79. IEEE, (2023)32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays.A. Santiccioli, M. Mercandelli, S. Dartizio, F. Tesolin, S. Karman, A. Shehata, L. Bertulessi, F. Buccoleri, L. Avallone, A. Parisi and 5 other author(s). ISSCC, page 456-458. IEEE, (2021)A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter.M. Mercandelli, A. Santiccioli, S. Dartizio, A. Shehata, F. Tesolin, S. Karman, L. Bertulessi, F. Buccoleri, L. Avallone, A. Parisi and 4 other author(s). ISSCC, page 445-447. IEEE, (2021)10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion.F. Tesolin, S. Dartizio, G. Castoro, F. Buccoleri, M. Rossoni, D. Cherniak, C. Samori, A. Lacaita, and S. Levantino. ISSCC, page 198-200. IEEE, (2024)A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching.S. Dartizio, F. Buccoleri, F. Tesolin, L. Avallone, A. Santiccioli, A. Iesurum, G. Steffan, D. Cherniak, L. Bertulessi, A. Bevilacqua and 3 other author(s). ISSCC, page 1-3. IEEE, (2022)A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology.G. Castoro, S. Dartizio, F. Tesolin, F. Buccoleri, M. Rossoni, D. Cherniak, L. Bertulessi, C. Samori, A. Lacaita, and S. Levantino. ISSCC, page 82-83. IEEE, (2023)A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler.F. Buccoleri, S. Dartizio, F. Tesolin, L. Avallone, A. Santiccioli, A. Iesurum, G. Steffan, A. Bevilacqua, L. Bertulessi, D. Cherniak and 3 other author(s). CICC, page 1-2. IEEE, (2022)

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Disambiguation of "Buccoleri, Francesco"