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10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion.

F. Tesolin, S. Dartizio, G. Castoro, F. Buccoleri, M. Rossoni, D. Cherniak, C. Samori, A. Lacaita, and S. Levantino. ISSCC, page 198-200. IEEE, (2024)

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Leonardo Estupiñán

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Other publications of authors with the same name

A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique.R. Moleri, S. Dartizio, M. Rossoni, G. Castoro, F. Tesolin, D. Cherniak, C. Samori, A. Lacaita, and S. Levantino. VLSI Technology and Circuits, page 1-2. IEEE, (2024)10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM.M. Rossoni, S. Dartizio, F. Tesolin, G. Castoro, R. Dell'Orto, C. Samori, A. Lacaita, and S. Levantino. ISSCC, page 188-190. IEEE, (2024)A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter.M. Mercandelli, A. Santiccioli, S. Dartizio, A. Shehata, F. Tesolin, S. Karman, L. Bertulessi, F. Buccoleri, L. Avallone, A. Parisi and 4 other author(s). ISSCC, page 445-447. IEEE, (2021)A 20MHz-BW 12.3-ENOB NS SAR ADC with a 3rd-order Multi-Input Filter and a PVT-Robust Ratio-Based FIA.G. Zanoletti, G. Bè, M. Rocco, L. Ricci, A. Ceroni, S. Levantino, A. Lacaita, L. Bertulessi, A. Bonfanti, and C. Samori. CICC, page 1-3. IEEE, (2025)A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching.S. Dartizio, F. Buccoleri, F. Tesolin, L. Avallone, A. Santiccioli, A. Iesurum, G. Steffan, D. Cherniak, L. Bertulessi, A. Bevilacqua and 3 other author(s). ISSCC, page 1-3. IEEE, (2022)10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion.F. Tesolin, S. Dartizio, G. Castoro, F. Buccoleri, M. Rossoni, D. Cherniak, C. Samori, A. Lacaita, and S. Levantino. ISSCC, page 198-200. IEEE, (2024)34.2 A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS.S. Dartizio, G. Castoro, S. Gallucci, M. Rossoni, R. Moleri, F. Tesolin, P. Salvi, S. Karman, A. Lacaita, and S. Levantino. ISSCC, page 1-3. IEEE, (2025)34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning.S. Gallucci, F. Tesolin, P. Salvi, D. Rizzini, R. Moleri, F. Buccoleri, M. Rossoni, G. Castoro, S. Dartizio, C. Samori and 2 other author(s). ISSCC, page 558-560. IEEE, (2025)A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS.A. Garghetti, A. Lacaita, D. Seebacher, M. Bassi, and S. Levantino. CICC, page 1-2. IEEE, (2021)17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking.A. Santiccioli, M. Mercandelli, L. Bertulessi, A. Parisi, D. Cherniak, A. Lacaita, C. Samori, and S. Levantino. ISSCC, page 268-270. IEEE, (2020)

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Disambiguation of "Lacaita, Andrea Leonardo"