From post

копировать удалить добавить публикацию в буфер
Запись сообщества
посмотреть историю данной записи
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment.

D. Kwai, Y. Chou, M. Chang, S. Yang, D. Chen, M. Hsu, Y. Liao, S. Lin, Y. Sung, C. Lee, и H. Hsu. MTDT, стр. 28-33. IEEE Computer Society, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Fan Chen Meng

Meng-Chang Liu

Meng Meng

Meng Meng Liang

Meng Zhang

Methods and implementations of road-network matchingM. Zhang. TU München, (2009)

Другие публикации лиц с тем же именем

Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices.K. Tang, W. Wei, Z. Yeh, T. Hsu, Y. Chiu, C. Xue, Y. Kuo, T. Wen, M. Ho, C. Lo и 3 other автор(ы). VLSI Circuits, стр. 166-. IEEE, (2019)5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel.T. Hsu, Y. Chen, J. Wu, W. Ting, C. Wang, C. Yeh, S. Sie, Y. Chen, R. Liu, C. Lo и 3 other автор(ы). ISSCC, стр. 110-112. IEEE, (2020)13.4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices.T. Chang, Y. Chiu, C. Lee, J. Hung, K. Chang, C. Xue, S. Wu, H. Kao, P. Chen, H. Huang и 2 other автор(ы). ISSCC, стр. 224-226. IEEE, (2020)14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse.J. Yue, Z. Yuan, X. Feng, Y. He, Z. Zhang, X. Si, R. Liu, M. Chang, X. Li, H. Yang и 1 other автор(ы). ISSCC, стр. 234-236. IEEE, (2020)eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache.K. Yang, H. Tsai, C. Li, P. Jendra, M. Chang, и T. Chen. IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (4): 858-868 (2017)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques.M. Chang, M. Chen, L. Chen, S. Yang, Y. Kuo, J. Wu, H. Su, Y. Chu, W. Wu, T. Yang и 1 other автор(ы). IEEE J. Solid State Circuits, 48 (10): 2558-2569 (2013)Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements.M. Chang, S. Yang, C. Liang, C. Chiang, P. Chiu, и K. Lin. IEEE J. Solid State Circuits, 45 (10): 2142-2155 (2010)A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors.A. Lee, C. Lo, C. Lin, W. Chen, K. Hsu, Z. Wang, F. Su, Z. Yuan, Q. Wei, Y. King и 8 other автор(ы). IEEE J. Solid State Circuits, 52 (8): 2194-2207 (2017)A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification.T. Hsu, G. Chen, Y. Chen, R. Liu, C. Lo, K. Tang, M. Chang, и C. Hsieh. IEEE J. Solid State Circuits, 58 (11): 3266-3274 (ноября 2023)A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.Z. Wang, Y. Liu, A. Lee, F. Su, C. Lo, Z. Yuan, J. Li, C. Lin, W. Chen, H. Chiu и 7 other автор(ы). IEEE J. Solid State Circuits, 52 (10): 2769-2785 (2017)

BibSonomy

Disambiguation