( en | de | ru )

 

Disambiguation of "Kuga, Morihiro"

Author of the publication

copydeleteadd this publication to your clipboard
SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks.

, , , , , and . COOL CHIPS, page 1-6. IEEE, (2024)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ieva Stupp-Kuga

 

Other publications of authors with the same name

Power-aware FPGA routing fabrics and design tools., , , , , and . VLSI-SoC, page 67-72. IEEE, (2010)EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA., , , , , and . FPT, page 209-216. IEEE, (2004)Blokus Duo engine on a Zynq., , , , , and . FPT, page 374-377. IEEE, (2014)hCODE: An open-source platform for FPGA accelerators., , , , , and . FPT, page 205-208. IEEE, (2016)Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration., , , , , , and . ICA3PP (1), volume 7439 of Lecture Notes in Computer Science, page 392-404. Springer, (2012)A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration., , , , and . ICA3PP (1), volume 7439 of Lecture Notes in Computer Science, page 139-152. Springer, (2012)A novel physical defects recovery technique for FPGA-IP cores., , , , , and . ReConFig, page 1-7. IEEE, (2012)An automatic FPGA design and implementation framework., , , , and . FPL, page 1-4. IEEE, (2013)A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory., , , , , and . FPL, page 1-6. IEEE, (2014)High-level Synthesis based on Parallel Design Patterns using a Functional Language., , , , and . HEART, page 23:1-23:6. ACM, (2017)