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iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor., , , , and . DAC, page 90-95. ACM, (2008)On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform., , , , and . IEEE Trans. Circuits Syst. Video Techn., 17 (7): 814-822 (2007)Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture., , , , and . SiPS, page 428-433. IEEE, (2006)Application Layer Error Correction Scheme for Video Header Protection on Wireless Network., , , , , and . ISM, page 499-505. IEEE Computer Society, (2005)Scalable Rate-Distortion-Computation Hardware Accelerator for MCTF and ME., , , and . ICME, page 365-368. IEEE Computer Society, (2006)Diastolic arrays: throughput-driven reconfigurable computing., , , , and . ICCAD, page 457-464. IEEE Computer Society, (2008)Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine., , , , , and . IEEE Trans. Circuits Syst. Video Techn., 18 (1): 98-109 (2008)Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT., , , , and . ISCAS (5), page 5190-5193. IEEE, (2005)Frame-level data reuse for motion-compensated temporal filtering., , , and . ISCAS, IEEE, (2006)Line Buffer Wordlength Analysis for Line-Based 2-D DWT., , , and . ICASSP (3), page 924-927. IEEE, (2006)