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A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST.

D. Anand, J. Covino, J. Dreibelbis, J. Fifield, K. Gorman, M. Jacunski, J. Paparelli, G. Pomichter, D. Pontius, M. Roberge, and S. Sliva. CICC, page 795-798. IEEE, (2007)

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Davinder Kumar Anand

Darren Gould

Darren Goins

Amar Frank Anand

Madhankumar Anandhakrishnan

Other publications of authors with the same name

Shared fuse macro for multiple embedded memory devices with redundancy.M. Ouellette, D. Anand, and P. Jakobsen. CICC, page 191-194. IEEE, (2001)14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming.E. Hunt-Schroeder, D. Anand, J. Fifield, M. Jacunski, M. Roberge, D. Pontius, K. Batson, and T. Kirihata. VLSI Circuits, page 87-88. IEEE, (2018)An On-Chip Self-Repair Calculation and Fusing Methodology.D. Anand, B. Cowan, O. Farnsworth, P. Jakobsen, S. Oakland, M. Ouellette, and D. Wheater. IEEE Des. Test Comput., 20 (5): 67-75 (2003)Behavioral Modeling of a Charge Trap Transistor One Time Programmable Memory.E. Hunt-Schroeder, D. Anand, E. Hwang, A. Cummings, M. Deming, M. Roberge, and M. Ziegerhofer. NATW, page 1-6. IEEE, (2019)A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns.M. Jacunski, D. Anand, R. Busch, J. Fifield, M. Lanahan, P. Lane, A. Paparelli, G. Pomichter, D. Pontius, M. Roberge and 1 other author(s). CICC, page 1-4. IEEE, (2010)A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface.H. Pilo, D. Anand, J. Barth, S. Burns, P. Corson, J. Covino, and S. Lamphier. IEEE J. Solid State Circuits, 38 (11): 1974-1980 (2003)Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering.J. Jr., J. Dreibelbis, E. Nelson, D. Anand, G. Pomichter, P. Jakobsen, M. Nelms, J. Leach, and G. Belansek. IBM J. Res. Dev., 46 (6): 675-690 (2002)Embedded DRAM built in self test and methodology for test insertion.P. Jakobsen, J. Dreibelbis, G. Pomichter, D. Anand, J. Barth, M. Nelms, J. Leach, and G. Belansek. ITC, page 975-984. IEEE Computer Society, (2001)Low Cost Test of High Bandwidth Embedded Memories.K. Gorman, D. Anand, G. Pomichter, and W. Corbin. CICC, page 445-448. IEEE, (2006)Generating At-Speed Array Fail Maps with Low-Speed ATE.M. Nelms, K. Gorman, and D. Anand. VTS, page 87-96. IEEE Computer Society, (2004)

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Disambiguation of "Anand, Darren"

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A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST.

Please choose a person to relate this publication to

Davinder Kumar Anand

Darren Gould

Darren Goins

Amar Frank Anand

Madhankumar Anandhakrishnan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Anand, Darren"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST.

Please choose a person to relate this publication to

Davinder Kumar Anand

Darren Gould

Darren Goins

Amar Frank Anand

Madhankumar Anandhakrishnan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST.