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Disambiguation of "Panades, Ivan Miro"

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SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency.

, , , , , , , , , , , , , , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)

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Miro Klampfer

Miro Venturi

Miro Uran

Miro Spönemann

Miro Brajenovic

 

Other publications of authors with the same name

Benefits of Joint Optimization of Tunable Wake-up Radio Architecture and Protocols., , , , , , , and . ICECS, page 789-792. IEEE, (2018)Freezer: A Specialized NVM Backup Controller for Intermittently Powered Systems., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (8): 1559-1572 (2021)SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration., , , , , , , , , and 10 other author(s). IEEE J. Solid State Circuits, 58 (6): 1782-1797 (2023)Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture., , , and . NOCS, page 139-148. IEEE Computer Society, (2008)Shadow-scan design with low latency overhead and in-situ slack-time monitoring., , , , , , and . ETS, page 1-6. IEEE, (2014)Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture., , and . DATE, page 1090-1095. EDA Consortium, San Jose, CA, USA, (2007)A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach., , and . Nano-Net, page 1-5. IEEE, (2006)Architectural exploration of a fine-grained 3D cache for high performance in a manycore context., , and . VLSI-SoC, page 302-307. IEEE, (2013)Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures., and . NOCS, page 83-94. IEEE Computer Society, (2007)3D stacking for multi-core architectures: From WIDEIO to distributed caches., , , , and . ISCAS, page 537-540. IEEE, (2013)