From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

Architecture of Cobweb-Based Redundant TSV for Clustered Faults., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 28 (7): 1736-1739 (2020)Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS., , , , , , , и . IEEE Trans. Emerg. Top. Comput., 9 (1): 520-533 (2021)Design of a Novel Self-Recoverable SRAM Cell Protected Against Soft Errors., , , , , и . DSA, стр. 497-498. IEEE, (2019)Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications., , , , , , , и . ACM Great Lakes Symposium on VLSI, стр. 293-298. ACM, (2023)Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory., , , , , , и . VTS, стр. 1-6. IEEE, (2019)Aging-Temperature-and-Propagation Induced Pulse-Broadening Aware Soft Error Rate Estimation for nano-Scale CMOS., , , , и . ATS, стр. 86-91. IEEE, (2018)IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications., , , , , , , и . ACM Great Lakes Symposium on VLSI, стр. 19-24. ACM, (2024)MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method., , , , , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (7): 2205-2214 (июля 2024)Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique., , , , , и . ITC-Asia, стр. 49-54. IEEE, (2018)Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications., , , , , , , , и . IEEE Trans. Aerosp. Electron. Syst., 58 (1): 517-529 (2022)