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A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , и . VLSI Circuits, стр. 1-2. IEEE, (2020)

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Shih-Hsien Kuo

Shih-Kung Lo

Yichang Shih

Linda Hsien

Shih-En Shih

 

Другие публикации лиц с тем же именем

Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits., , , , , , и . ISQED, стр. 410-415. IEEE Computer Society, (2005)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference., , , , , , , , , и 33 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2020)High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header., , и . VLSI Design, стр. 758-761. IEEE Computer Society, (2006)Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices., , , , , , и . Microelectron. J., 38 (8-9): 931-941 (2007)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference., , , , , , , , , и 21 other автор(ы). VLSI Circuits, стр. 35-36. IEEE, (2018)Across the Stack Opportunities for Deep Learning Acceleration., , , , , , , , , и 21 other автор(ы). ISLPED, стр. 35:1-35:2. ACM, (2018)Efficient AI System Design With Cross-Layer Approximate Computing., , , , , , , , , и 30 other автор(ы). Proc. IEEE, 108 (12): 2232-2250 (2020)