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Disambiguation of "Sakimura, Noboru"

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Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS.

, , , , , , , , , , , and . ISSCC, page 228-229. IEEE, (2011)

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Noboru Yamazaki

Noboru Sonoyama

Noboru Hasegawa

Sergio Noboru Kuriyama

 

Other publications of authors with the same name

Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode., , , , , and . IEICE Trans. Electron., 90-C (2): 531-535 (2007)A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes., , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2013)Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating., , , , , , , , , and 4 other author(s). ISSCC, page 194-195. IEEE, (2013)MRAM Cell Technology for Over 500-MHz SoC., , , , , , , and . IEEE J. Solid State Circuits, 42 (4): 830-838 (2007)A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing., , , , , , , , , and 5 other author(s). ISCAS, page 1588-1591. IEEE, (2014)A non-volatile reconfigurable offloader for wireless sensor nodes., , , , and . SIGARCH Comput. Archit. News, 40 (5): 87-92 (2012)A 90nm 12ns 32Mb 2T1MTJ MRAM., , , , , , , , , and 10 other author(s). ISSCC, page 462-463. IEEE, (2009)Soft-Delay-Error Evaluation in Content-Addressable Memory., , , , , and . ISMVL, page 220-225. IEEE Computer Society, (2014)High-speed simulator including accurate MTJ models for spintronics integrated circuit design., , , , , , , , , and 1 other author(s). ISCAS, page 1971-1974. IEEE, (2012)Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS., , , , , , , , , and 2 other author(s). ISSCC, page 228-229. IEEE, (2011)