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Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.

Y. Zhang, C. Zhang, J. Nan, Z. Zhang, X. Zhang, J. Klein, D. Ravelosona, G. Sun, and W. Zhao. IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (5): 629-638 (2016)

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High Performance SoC Design Using Magnetic Logic and Memory.W. Zhao, L. Torres, L. Cargnini, R. Brum, Y. Zhang, Y. Guillemenet, G. Sassatelli, Y. Lakys, J. Klein, D. Etiemble and 2 other author(s). VLSI-SoC (Selected Papers), volume 379 of IFIP Advances in Information and Communication Technology, page 10-33. Springer, (2011)Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires.N. Romdhane, W. Zhao, Y. Zhang, J. Klein, Z. Wang, and D. Ravelosona. NANOARCH, page 71-76. IEEE Computer Society/ACM, (2014)Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology.W. Kang, Y. Zhang, Z. Wang, J. Klein, C. Chappert, D. Ravelosona, G. Wang, Y. Zhang, and W. Zhao. ACM J. Emerg. Technol. Comput. Syst., 12 (2): 16:1-16:42 (2015)An overview of spin-based integrated circuits.W. Kang, W. Zhao, Z. Wang, J. Klein, Y. Zhang, D. Chabi, Y. Zhang, D. Ravelosona, and C. Chappert. ASP-DAC, page 676-683. IEEE, (2014)One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories.W. Kang, W. Zhao, L. Yang, J. Klein, Y. Zhang, and D. Ravelosona. NVMSA, page 1-6. IEEE, (2014)Perspectives of racetrack memory based on current-induced domain wall motion: From device to system.Y. Zhang, C. Zhang, J. Klein, D. Ravelosona, G. Sun, and W. Zhao. ISCAS, page 381-384. IEEE, (2015)Spin-electronics based logic fabrics.W. Zhao, J. Klein, Z. Wang, Y. Zhang, N. Romdhane, D. Querlioz, D. Ravelosona, and C. Chappert. VLSI-SoC, page 174-179. IEEE, (2013)Synchronous full-adder based on complementary resistive switching memory cells.Y. Zhang, E. Deng, J. Klein, D. Querlioz, D. Ravelosona, C. Chappert, W. Zhao, M. Moreau, J. Portal, M. Bocquet and 3 other author(s). NEWCAS, page 1-4. IEEE, (2013)Ultra-Dense Ring-Shaped Racetrack Memory Cache Design.G. Wang, Y. Zhang, B. Zhang, B. Wu, J. Nan, X. Zhang, Z. Zhang, J. Klein, D. Ravelosona, Z. Wang and 2 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (1): 215-225 (2019)Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.W. Zhao, J. Portal, W. Kang, M. Moreau, Y. Zhang, H. Aziza, J. Klein, Z. Wang, D. Querlioz, D. Deleruyelle and 4 other author(s). J. Parallel Distributed Comput., 74 (6): 2484-2496 (2014)

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Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.

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Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.