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A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (3): 1077-1081 (March 2024)Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells., , , , , , , , , and 4 other author(s). J. Parallel Distributed Comput., 74 (6): 2484-2496 (2014)Magnetic memory (MRAM), a new area for 2D and 3D SoC/SiP design., and . ACM Great Lakes Symposium on VLSI, page 429-430. ACM, (2011)S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks., , , , , and . CoRR, (2021)Work-in-Progress: Toward Energy-efficient Near STT-MRAM Processing Architecture for Neural Networks., , , , , and . CODES+ISSS, page 13-14. IEEE, (2022)Fully Single Event Double Node Upset Tolerant Design for Magnetic Random Access Memory., , , , , , , , , and 1 other author(s). ISCAS, page 1-5. IEEE, (2021)A Novel In-memory Computing Scheme Based on Toggle Spin Torque MRAM., , , , , , , and . ACM Great Lakes Symposium on VLSI, page 351-356. ACM, (2020)TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning., , , , , , and . DAC, page 1-6. IEEE, (2023)Magnetic skyrmions for future potential memory and logic applications: Alternative information carriers., , , , , , and . DATE, page 119-124. IEEE, (2018)Spintronics for low-power computing., , , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)