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A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder., , , , and . ASICON, page 1-4. IEEE, (2013)A 2D mesh NoC with self-configurable and shared-FIFOs routers., , , , and . ASICON, page 1-4. IEEE, (2013)Low-complexity two-stage timing acquisition scheme for UWB communications., , and . WTS, page 53-56. IEEE, (2008)A fast multi-core virtual platform and its application on software development., , , , and . ASICON, page 1-4. IEEE, (2013)Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications., , , , and . ASICON, page 465-468. IEEE, (2011)Quarter LCU based integer motion estimation algorithm for HEVC., , , and . ICIP, page 2018-2021. IEEE, (2016)Low power design for FIR filter., , , and . ASICON, page 1-4. IEEE, (2013)Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation., , , and . SiPS, page 151-156. IEEE, (2007)Fp2 arithmetic acceleration based on modified Barrett modular multiplication algorithm., , , and . ASICON, page 561-564. IEEE, (2017)Optimized digital automatic gain control for DVB-S2 system., , , , and . WTS, page 1-5. IEEE, (2010)