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Systematical study of 14nm FinFET reliability: From device level stress to product HTOL.

, , , , , , , , , , , , и . IRPS, стр. 2. IEEE, (2015)

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Hyun-Chul Kim

Hyun-Chul Cho

Hee Hyun

Rajani Chulyadyo

Tae Kyung Hyun

 

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Effects of Far-BEOL anneal on the WLR and product reliability characterization of FinFET process technology., , , , , , , , , и 1 other автор(ы). IRPS, стр. 6. IEEE, (2018)Investigation of alpha-induced single event transient (SET) in 10 nm FinFET logic circuit., , , , , , , и . IRPS, стр. 1. IEEE, (2018)A systematic study of gate dielectric TDDB in FinFET technology., , , , , , , , и . IRPS, стр. 4. IEEE, (2018)Reliability characterization of advanced CMOS image sensor (CIS) with 3D stack and in-pixel DTI., , , , , , , , , и 10 other автор(ы). IRPS, стр. 3. IEEE, (2018)Advanced Self-heating Model and Methodology for Layout Proximity Effect in FinFET Technology., , , , , , , , , и 3 other автор(ы). IRPS, стр. 1-5. IEEE, (2020)Systematical study of 14nm FinFET reliability: From device level stress to product HTOL., , , , , , , , , и 3 other автор(ы). IRPS, стр. 2. IEEE, (2015)Localized Layout Effect Related Reliability Approach in 8nm FinFETs Technology: From Transistor to Circuit., , , , , и . IRPS, стр. 1-5. IEEE, (2019)