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Area-efficient pipelining for FPGA-targeted high-level synthesis.

, , , and . DAC, page 157:1-157:6. ACM, (2015)

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Architecture and synthesis for multi-cycle on-chip communication., , , , and . CODES+ISSS, page 77-78. ACM, (2003)GraphZoom: A Multi-level Spectral Approach for Accurate and Scalable Graph Embedding., , , , and . ICLR, OpenReview.net, (2020)Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (11): 1817-1830 (2017)Special Session: Machine Learning for Embedded System Design., , , , , , , , , and 1 other author(s). CODES+ISSS, page 28-37. IEEE, (2023)Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks., , , , , and . ASP-DAC, page 152-157. ACM, (2021)Enabling adaptive loop pipelining in high-level synthesis., , , and . ACSSC, page 131-135. IEEE, (2017)High-level synthesis with timing-sensitive information flow enforcement., , , and . ICCAD, page 88. ACM, (2018)PokeBNN: A Binary Pursuit of Lightweight Accuracy., , and . CVPR, page 12465-12475. IEEE, (2022)An efficient and versatile scheduling algorithm based on SDC formulation., and . DAC, page 433-438. ACM, (2006)A reconfigurable analog substrate for highly efficient maximum flow computation., and . DAC, page 17:1-17:6. ACM, (2015)