( en | de | ru )

 

Disambiguation of "Shibata, Hajime"

Author of the publication

copydeleteadd this publication to your clipboard
Analog circuit synthesis by superimposing of sub-circuits.

, and . ISCAS (5), page 427-430. IEEE, (2001)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hajime Sakai

Daisuke Shibata

Tomohiro Shibata

Hajime Konno

Hajime Myoken

 

Other publications of authors with the same name

A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS., , , and . CICC, page 1-4. IEEE, (2017)Frequency Response Analysis of Latch Utilized in High-Speed Comparator., , , and . ICECS, page 1077-1080. IEEE, (2006)A DC-to-1 GHz Tunable RF Delta Sigma ADC Achieving DR = 74 dB and BW = 150 MHz at f0 = 450 MHz Using 550 mW., , , , , , , and . IEEE J. Solid State Circuits, 47 (12): 2888-2897 (2012)A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET., , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Automated Design of Analog Circuits Using Cell-Based Structure ., , and . Evolvable Hardware, page 85-92. IEEE Computer Society, (2002)A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs., , , , , , , , , and 1 other author(s). CICC, page 1-2. IEEE, (2023)15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS., , , , , , , , , and . ISSCC, page 278-279. IEEE, (2016)Measurement System for Switching Current Distribution in Intrinsic Josephson Junctions., , , , and . IEICE Trans. Electron., 90-C (3): 605-606 (2007)A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers., , , and . IEEE J. Solid State Circuits, 53 (3): 681-691 (2018)A -89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (7): 859-863 (2018)