Author of the publication

RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy.

, , , , , , , and . CoRR, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (4): 986-998 (2022)Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks., , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (2): 34:1-34:22 (2022)T-BFA: Targeted Bit-Flip Adversarial Weight Attack., , , , , and . IEEE Trans. Pattern Anal. Mach. Intell., 44 (11): 7928-7939 (2022)Deep Learning for Moving Blockage Prediction using Real Millimeter Wave Measurements., , , , and . CoRR, (2021)Automated Parallel Kernel Extraction from Dynamic Application Traces., , and . CoRR, (2020)Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks., , , , , and . CoRR, (2021)Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs., , , , , and . IEEE Des. Test, 37 (6): 79-87 (2020)Data storage time sensitive ECC schemes for MLC NAND Flash memories., , , and . ICASSP, page 2513-2517. IEEE, (2013)Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression., , , , , and . CoRR, (2018)High sample rate array architectures for median filters.. IEEE Trans. Signal Process., 42 (3): 707-712 (1994)