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Data storage time sensitive ECC schemes for MLC NAND Flash memories., , , и . ICASSP, стр. 2513-2517. IEEE, (2013)Articulation constrained learning with application to speech emotion recognition., , , , и . EURASIP J. Audio Speech Music. Process., (2019)Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory., , , , , , , , , и 3 other автор(ы). IEEE J. Solid State Circuits, 57 (4): 986-998 (2022)Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks., , , , , и . ACM J. Emerg. Technol. Comput. Syst., 18 (2): 34:1-34:22 (2022)Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs., , , , , и . IEEE Des. Test, 37 (6): 79-87 (2020)Communication and Computation Reduction for Split Learning using Asynchronous Training., , и . SiPS, стр. 76-81. IEEE, (2021)Compressing LSTM Networks with Hierarchical Coarse-Grain Sparsity., , , , и . INTERSPEECH, стр. 21-25. ISCA, (2020)Improving Energy Efficiency of Convolutional Neural Networks on Multi-core Architectures through Run-time Reconfiguration., , , , , , и . ISCAS, стр. 375-379. IEEE, (2022)FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs)., , , , , , , , , и 5 other автор(ы). IEEE Des. Test, 41 (1): 70-80 (февраля 2024)System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration., , , , , и . ASICON, стр. 1-4. IEEE, (2021)