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8 Tbps Co-Packaged FPGA and Silicon Photonics Optical IO.

K. Hosseini, E. Kok, S. Shumarayev, C. Chiu, A. Sarkar, A. Toda, Y. Ke, A. Chan, D. Jeong, M. Zhang, S. Raman, T. Tran, K. Singh, P. Bhargava, C. Zhang, H. Lu, R. Mahajan, X. Li, N. Deshpande, C. O'Keeffe, T. Hoang, U. Krishnamoorthy, C. Sun, R. Meade, V. Stojanovic, and M. Wade. OFC, page 1-3. IEEE, (2021)

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Sergey Libert

Sergey Stepanov

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Sergey Rosbakh

Sergey Samsonov

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8 Tbps Co-Packaged FPGA and Silicon Photonics Optical IO.K. Hosseini, E. Kok, S. Shumarayev, C. Chiu, A. Sarkar, A. Toda, Y. Ke, A. Chan, D. Jeong, M. Zhang and 16 other author(s). OFC, page 1-3. IEEE, (2021)Silicon Photonics Chip I/O for Ultra High-Bandwidth and Energy-Efficient Die-to-Die Connectivity.Y. Wang, S. Wang, R. Parsons, A. Novick, V. Gopal, K. Jang, A. Rizzo, C. Chiu, K. Hosseini, T. Hoang and 2 other author(s). CICC, page 1-8. IEEE, (2024)Emerging standards at ∼10 Gbps for wireline communications and associated integrated circuit design and validation.M. Li, and S. Shumarayev. CICC, page 105-112. IEEE, (2009)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).E. Nurvitadhi, J. Cook, A. Mishra, D. Marr, K. Nealis, P. Colangelo, A. Ling, D. Capalija, U. Aydonat, S. Shumarayev and 1 other author(s). FPGA, page 287. ACM, (2018)Heterogenous Integration Enables FPGA Based Hardware Acceleration for RF Applications.S. Shumarayev, A. Chan, T. Hoang, and R. Keller. HCS, page 1-20. IEEE, (2022)On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing.W. Ding, M. Pan, W. Wong, D. Chow, M. Li, and S. Shumarayev. ITC, page 1-7. IEEE Computer Society, (2012)Receiver Offset Cancellation in 90-nm PLD Integrated SERDES.S. Maangat, T. Nguyen, W. Wong, S. Shumarayev, T. Tran, T. Hoang, and R. Cliff. CICC, page 265-267. IEEE, (2007)A signal integrity-based link performance simulation platform.Y. Tao, W. Bereza, R. Patel, S. Shumarayev, and T. Kwasniewski. CICC, page 725-728. IEEE, (2005)Arria™ 10 device architecture.J. Tyhach, M. Hutton, S. Atsatt, A. Rahman, B. Vest, D. Lewis, M. Langhammer, S. Shumarayev, T. Hoang, A. Chan and 8 other author(s). CICC, page 1-8. IEEE, (2015)Introducing 28-nm stratix VFPGAs: Built for bandwidth.D. Mansur, and S. Shumarayev. Hot Chips Symposium, page 1-23. IEEE, (2010)

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Disambiguation of "Shumarayev, Sergey Y."

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8 Tbps Co-Packaged FPGA and Silicon Photonics Optical IO.

Please choose a person to relate this publication to

Sergey Libert

Sergey Stepanov

Sergey Gorbunov

Sergey Rosbakh

Sergey Samsonov

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Shumarayev, Sergey Y."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 8 Tbps Co-Packaged FPGA and Silicon Photonics Optical IO.

Please choose a person to relate this publication to

Sergey Libert

Sergey Stepanov

Sergey Gorbunov

Sergey Rosbakh

Sergey Samsonov

Other publications of authors with the same name

Disambiguation

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URL
DOI
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8 Tbps Co-Packaged FPGA and Silicon Photonics Optical IO.