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Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262.

S. Wang, Y. Higami, H. Takahashi, H. Iwata, Y. Maeda, and J. Matsushima. ETS, page 1-2. IEEE, (2018)

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Yoshinobu Kumazawa

Other publications of authors with the same name

Dynamic routing and wavelength assignment in multifiber WDM networks with sparse wavelength conversion.Dewiani, K. Hirata, Y. Higami, and S. ya Kobayashi. ICTC, page 567-572. IEEE, (2012)Post-BIST Fault Diagnosis for Multiple Faults.H. Takahashi, Y. Higami, S. Kadoyama, Y. Takamatsu, K. Yamazaki, T. Aikyo, and Y. Sato. IEICE Trans. Inf. Syst., 91-D (3): 771-775 (2008)A Method to Find Don't Care Values in Test Sequences for Sequential Circuits.Y. Higami, S. ya Kobayashi, Y. Takamatsu, S. Kajihara, and I. Pomeranz. ICCD, page 397-. IEEE Computer Society, (2003)Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults.Y. Higami, K. Saluja, H. Takahashi, S. ya Kobayashi, and Y. Takamatsu. ATS, page 97-102. IEEE Computer Society, (2008)New Class of Tests for Open Faults with Considering Adjacent Lines.H. Takahashi, Y. Higami, Y. Takamatsu, K. Yamazaki, T. Tsutsumi, H. Yotsuyanagi, and M. Hashizume. Asian Test Symposium, page 301-306. IEEE Computer Society, (2009)Preliminary Study on Noise-Resilient Artificial Neural Networks for On-Chip Test Generation.T. Inamoto, T. Nishino, S. Wang, Y. Higami, and H. Takahashi. GCCE, page 561-565. IEEE, (2022)Enhancement of Clock Delay Faults Testing.Y. Higami, H. Takahashi, S. ya Kobayashi, and K. Saluja. ETS, page 216. IEEE Computer Society, (2011)Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits.Y. Higami, Y. Takamatsu, K. Saluja, and K. Kinoshita. Asian Test Symposium, page 141-146. IEEE Computer Society, (1999)Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits.Y. Higami, K. Saluja, and K. Kinoshita. Asian Test Symposium, page 312-317. IEEE Computer Society, (1998)Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation.Y. Higami, K. Saluja, H. Takahashi, and Y. Takamatsu. VLSI Design, page 781-786. IEEE Computer Society, (2007)

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Disambiguation of "Higami, Yoshinobu"

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Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262.

Please choose a person to relate this publication to

Yoshinobu Kumazawa

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Higami, Yoshinobu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262.

Please choose a person to relate this publication to

Yoshinobu Kumazawa

Other publications of authors with the same name

Disambiguation

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URL
DOI
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APA
Chicago
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Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262.