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Disambiguation of "Soumyanath, Krishnamurthy"

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A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application.

, , , , , and . IEEE J. Solid State Circuits, 46 (7): 1596-1605 (2011)

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Mahalakshmi Krishnamurthy

Adarsh Krishnamurthy

Arvind Krishnamurthy

Vittala Naranappa Krishnamurthy

 

Other publications of authors with the same name

A 3.6GHz, 16mW ΣΔ DAC for a 802.11n / 802.16e transmitter with 30dB digital power control in 90nm CMOS., , , , and . ESSCIRC, page 202-205. IEEE, (2008)Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends., , , , , and . IEEE J. Solid State Circuits, 36 (11): 1636-1646 (2001)A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS., , , , , and . ISSCC, page 70-72. IEEE, (2012)8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3rd order, 3/5-bit IIR and 3rd order 3-bit-FIR noise shapers in 90nm CMOS., , , and . CICC, page 625-628. IEEE, (2004)Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process., , , , , , , , , and 1 other author(s). CICC, page 617-620. IEEE, (2003)A 9-b 400 Msample/s pipelined analog-to digital converter in 90nm CMOS., , , , and . ESSCIRC, page 535-538. IEEE, (2005)A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS., , and . ESSCIRC, page 352-355. IEEE, (2007)A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS., , , , and . CICC, page 1-4. IEEE, (2009)Desensitized design of MOS low noise amplifiers by Rn minimization., , , , and . ICECS, page 619-622. IEEE, (2004)A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 44 (6): 1668-1678 (2009)