Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions.

K. Yamamoto, K. Ando, N. Mertig, T. Takemoto, M. Yamaoka, H. Teramoto, A. Sakai, S. Takamaeda-Yamazaki, and M. Motomura. ISSCC, page 138-140. IEEE, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Satoko Yamazaki

Shinya Sato

Shinya Minegishi

Noboru Yamazaki

Asuka Yamazaki

Other publications of authors with the same name

Cachet: Low-Overhead Integrity Verification on Metadata Cache in Secure Nonvolatile Memory Systems.T. Kubo, and S. Takamaeda-Yamazaki. IEEE Micro, 44 (1): 38-48 (January 2024)BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.K. Ando, K. Ueyoshi, K. Orimo, H. Yonekawa, S. Sato, H. Nakahara, S. Takamaeda-Yamazaki, M. Ikebe, T. Asai, T. Kuroda and 1 other author(s). IEEE J. Solid State Circuits, 53 (4): 983-994 (2018)Accelerating Decision Tree Ensemble with Guided Branch Approximation.K. Kamahori, and S. Takamaeda-Yamazaki. HEART, page 24-32. ACM, (2022)Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations.R. Kobayashi, S. Takamaeda-Yamazaki, and K. Kise. ICNC, page 343-349. IEEE Computer Society, (2012)FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects.A. Tanibata, A. Schmid, S. Takamaeda-Yamazaki, M. Ikebe, M. Motomura, and T. Asai. FPL, page 1. IEEE, (2017)Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing.A. Tanibata, A. Schmid, S. Takamaeda-Yamazaki, M. Ikebe, M. Motomura, and T. Asai. Complex., (2018)A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing.H. Vu, S. Takamaeda-Yamazaki, T. Nakada, and Y. Nakashima. IEICE Trans. Inf. Syst., 101-D (2): 288-302 (2018)Model-based Federated Reinforcement Distillation.S. Ryu, and S. Takamaeda-Yamazaki. GLOBECOM, page 1109-1114. IEEE, (2022)GeMP-BNN: High-Performance Sampling-Free Bayesian Neural Network Accelerator with Gaussian Error Moment Propagation.Y. Hirayama, K. Suga, and S. Takamaeda-Yamazaki. MCSoC, page 522-529. IEEE, (2023)Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL.S. Takamaeda-Yamazaki. ARC, volume 9040 of Lecture Notes in Computer Science, page 451-460. Springer, (2015)