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7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions.

, , , , , , , , и . ISSCC, стр. 138-140. IEEE, (2020)

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A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems., , , и . IEEE J. Solid State Circuits, 55 (1): 145-156 (2020)STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions., , , , , , , , , и . IEEE J. Solid State Circuits, 56 (1): 165-178 (2021)A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines., , , , , и . IEICE Trans. Inf. Syst., 102-D (9): 1696-1706 (2019)65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS., , , и . ISSCC, стр. 384-385. IEEE, (2008)Efficient Ising Model Mapping to Solving Slot Placement Problem., , , , , , , и . ICCE, стр. 1-6. IEEE, (2019)Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers., , и . ACM Great Lakes Symposium on VLSI, стр. 529-533. ACM, (2007)Technology/circuits joint evening panel discussion semiconductor industry in 2020: Evolution or revolution?, , , , , , , , , и 3 other автор(ы). VLSIC, стр. 22-. IEEE, (2015)Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing., , , и . Int. J. Netw. Comput., 7 (2): 154-172 (2017)A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation., , , , , и . CICC, стр. 701-704. IEEE, (2009)90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique., , , , , , , и . IEEE J. Solid State Circuits, 41 (3): 705-711 (2006)