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Disambiguation of "Murugesan, Mariappan"

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Development of via-last 3D integration technologies using a new temporary adhesive system.

, , , , and . 3DIC, page 1-4. IEEE, (2013)

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Kalaimathi Murugesan

Aruljothi Mariappan

Mariappan Sakthivel

Malaiyalam Mariappan

Manju Shrii Murugesan

 

Other publications of authors with the same name

Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology., , , , , and . 3DIC, page 1-4. IEEE, (2016)Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-Integration., , , , and . 3DIC, page 1-4. IEEE, (2019)Impact of Super-long-throw PVD on TSV Metallization and Die-to-Wafer 3D Integration Based on Via-last., , , , , , , , and . 3DIC, page 1-4. IEEE, (2023)Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration., , , , , , , , and . 3DIC, page 1-5. IEEE, (2009)Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO2 for Low-Temperature TSV Liner Formation., , , , , , , and . 3DIC, page 1-4. IEEE, (2019)Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV., , , , , , , and . 3DIC, page 1-4. IEEE, (2014)Micro-XRD investigation of fine-pitch Cu-TSV induced thermo-mechanical stress in high-density 3D-LSI., , , , , , , and . 3DIC, page 1-4. IEEE, (2014)W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress., , , , , and . 3DIC, page 1-4. IEEE, (2011)Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing., , , , , , , , , and . 3DIC, page 1-4. IEEE, (2021)New concept of TSV formation methodology using Directed Self-Assembly (DSA)., , , , , , , and . 3DIC, page 1-4. IEEE, (2016)