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Ultra low voltage design considerations of SOI SRAM memory cells., и . ISCAS (4), стр. 4094-4097. IEEE, (2005)Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology., , и . ISCAS, стр. 2778-2781. IEEE, (2007)Design, Fabrication and Dynamic Testing of Insect-Inspired Nano Air Vehicles., , , , , , , , и . MIXDES, стр. 17-22. IEEE, (2023)Thermo-mechanical study of a 2.5D passive silicon interposer technology: Experimental, numerical and In-Situ stress sensors developments., , , , , , , , , и 1 other автор(ы). 3DIC, стр. 1-7. IEEE, (2013)ExPACO: detection of an extended pattern under nonstationary correlated noise by patch covariance modeling., , , , и . EUSIPCO, стр. 1-5. IEEE, (2019)Design challenges for nano-scale devices., , , и . ESSDERC, стр. 69-72. IEEE, (2012)Resistive memories: Which applications?, , , , , , , , и . DATE, стр. 1-6. European Design and Automation Association, (2014)Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI., , , , и . ESSDERC, стр. 94-97. IEEE, (2014)OxRAM-based non volatile flip-flop in 28nm FDSOI., , , , , и . NEWCAS, стр. 141-144. IEEE, (2014)Stress management strategy to limit die curvature during silicon interposer integration., , , , , , , , , и 1 other автор(ы). 3DIC, стр. TS11.4.1-TS11.4.7. IEEE, (2015)