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A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.

, , , , , , , , , , и . CICC, стр. 1-4. IEEE, (2011)

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Zviel Friedman

Alexander Friedman

Ariell Friedman

Michel Friedman

Daniel J Schad

 

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An Integral Path Self-Calibration Scheme for a Dual-Loop PLL., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 48 (4): 996-1008 (2013)7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication., , , , , , , , , и 10 other автор(ы). ISSCC, стр. 128-129. IEEE, (2017)A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI., , , , и . CICC, стр. 431-434. IEEE, (2008)Ultra-low-power analog design.. ISSCC, стр. 526-527. IEEE, (2017)All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs., , , и . ISSCC, стр. 176-595. IEEE, (2007)A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS., , , , , , и . ISSCC, стр. 98-99. IEEE, (2009)An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS., , , , , , , , , и 1 other автор(ы). VLSIC, стр. 176-177. IEEE, (2012)Characterization of 14nm CMOS Technology At Cryogenic Temperatures Using Dense Addressable Arrays., , , , , и . VTS, стр. 1-7. IEEE, (2024)10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs., , , , и . ISSCC, стр. 196-198. IEEE, (2016)A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI., , , , , , , и . ISSCC, стр. 400-401. IEEE, (2013)