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Disambiguation of "Chang, Meng-Fan"

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A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications.

, , , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (4): 662-666 (2019)

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Fan Chen Meng

Meng-Chang Liu

Meng Meng

Meng Meng Liang

Meng Zhang

Methods and implementations of road-network matching. TU München, (2009)
 

Other publications of authors with the same name

5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel., , , , , , , , , and 3 other author(s). ISSCC, page 110-112. IEEE, (2020)13.4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices., , , , , , , , , and 2 other author(s). ISSCC, page 224-226. IEEE, (2020)14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse., , , , , , , , , and 1 other author(s). ISSCC, page 234-236. IEEE, (2020)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (10): 2558-2569 (2013)Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements., , , , , and . IEEE J. Solid State Circuits, 45 (10): 2142-2155 (2010)eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (4): 858-868 (2017)A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 52 (8): 2194-2207 (2017)A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification., , , , , , , and . IEEE J. Solid State Circuits, 58 (11): 3266-3274 (November 2023)A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 52 (10): 2769-2785 (2017)A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 59 (1): 52-64 (January 2024)