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19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS.

J. Zhu, R. Nandwana, G. Shu, A. Elkholy, S. Kim, and P. Hanumolu. ISSCC, page 338-340. IEEE, (2016)

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Guanghua Lin

Guanghua Du

Lijin Shu

Shu Zhang

Changshan Shu

Other publications of authors with the same name

An Embedding-Based Grocery Search Model at Instacart.Y. Xie, T. Na, X. Xiao, S. Manchanda, Y. Rao, Z. Xu, G. Shu, E. Vasiete, T. Tenneti, and H. Wang. CoRR, (2022)3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS.W. Choi, G. Shu, M. Talegaonkar, Y. Liu, D. Wei, L. Benini, and P. Hanumolu. ISSCC, page 1-3. IEEE, (2015)A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS.J. Zhu, M. Mahalley, G. Shu, W. Choi, R. Nandwana, A. Elkholy, B. Sahoo, and P. Hanumolu. CICC, page 1-4. IEEE, (2017)Design Considerations of Monolithically Integrated Voltage Regulators for Multicore Processors.H. Moghadam, J. Jang, M. Dayringer, T. Rak amnouykit, G. Shu, A. Yakovlev, Y. Zhang, and D. Hopkins. ISCAS, page 1-5. IEEE, (2018)15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS.A. Elkholy, A. Elshazly, S. Saxena, G. Shu, and P. Hanumolu. ISSCC, page 272-273. IEEE, (2014)A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS.M. Ahmed, M. Talegaonkar, A. Elkholy, G. Shu, A. Elmallah, A. Rylyakov, and P. Hanumolu. IEEE J. Solid State Circuits, 53 (2): 445-457 (2018)A 0.7V time-based inductor for fully integrated low bandwidth filter applications.B. Salz, M. Talegaonkar, G. Shu, A. Elmallah, R. Nandwana, B. Sahoo, and P. Hanumolu. CICC, page 1-4. IEEE, (2017)A 0.22 pJ/step subsampling ADC with fast input-tracking sampling and simplified opamp sharing.G. Shu, F. Ye, Y. Guo, M. Fan, J. Ren, J. Xu, N. Li, and C. Chen. ISCAS, page 3016-3019. IEEE, (2010)Energy-efficient wireline transceiversG. Shu. University of Illinois Urbana-Champaign, USA, (2016)23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS.G. Shu, W. Choi, S. Saxena, S. Kim, M. Talegaonkar, R. Nandwana, A. Elkholy, D. Wei, T. Nandi, and P. Hanumolu. ISSCC, page 398-399. IEEE, (2016)

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Disambiguation of "Shu, Guanghua"

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19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS.

Please choose a person to relate this publication to

Guanghua Lin

Guanghua Du

Lijin Shu

Shu Zhang

Changshan Shu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Shu, Guanghua"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS.

Please choose a person to relate this publication to

Guanghua Lin

Guanghua Du

Lijin Shu

Shu Zhang

Changshan Shu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS.