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GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches.

, , and . DAC, page 318-323. IEEE, (2007)

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Performance-driven mapping for CPLD architectures., , , and . FPGA, page 39-47. ACM, (2001)Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 650-663 (2016)Introduction.. ACM Trans. Reconfigurable Technol. Syst., 9 (4): 28:1-28:2 (2016)Algorithm/Accelerator Co-Design and Co-Search for Edge AI., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (7): 3064-3070 (2022)VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization., , , , , and . IEEE Trans. Computers, 70 (5): 696-710 (2021)ScaleHLS: Scalable High-Level Synthesis through MLIR., , , , , , and . CoRR, (2021)ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation., , , , , , and . HPCA, page 741-755. IEEE, (2022)FSSD: FPGA-Based Emulator for SSDs., , , , , , , and . FPL, page 101-108. IEEE, (2023)Decision-Making Behavior Evaluation Framework for LLMs under Uncertain Context., , , , and . CoRR, (2024)SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems., , , , , , , , , and 2 other author(s). MLSys, mlsys.org, (2020)